1. Field of the Invention
The present invention relates to a variable frequency divider circuit, and in particular, to a structure of a variable frequency divider circuit capable of changing its division ratio between F and F+1 with F being a natural number. Specifically, the present invention relates to a high-speed frequency divider (prescaler) circuit formed through. CMOS process.
2. Description of the Background Art
In recent years, the miniaturization of components in the CMOS (complementary metal-insulating film-semiconductor) process is progressed, to make it possible to manufacture a circuit for processing RF (radio frequency) band signals, which operates at a GHz (giga-hertz) speed, such as a PLL (phase locked loop) synthesizer.
FIG. 13 is a diagram representing a conventional high-speed frequency divider. FIG. 13 shows, as one example of high-speed frequency dividers, the structure of a prescaler in which its frequency division ratio can be changed between 1/4 and 1/5. When the frequency division ratio of the prescaler is 1/F, the frequency of the output signal thereof is 1/F times that of an input signal.
In FIG. 13, the prescaler includes three cascaded flip-flops 1-3. In the flip-flops 2 and 3, their output signals FBA and FBB are fed back to the first stage flip-flop 1. Complementary output signals OUT and OUTB are outputted through output terminals 9 and 10 from the first stage flip-flop 1. Each of the flip-flops 1-3 performs transfer/latch operation of the feedback signals FBA and FBB in accordance with complementary input signals ZIN and IN applied to terminals 6 and 7 to generate frequency-divided signals OUT and OUTB of the input signals IN and ZIN.
The flip-flop 1 includes two cascaded latch circuits LT1 and LT2 performing transfer/latch operation complementarily to each other in accordance with the input signals IN and ZIN. The latch circuit LT1 includes: resistance elements 11a and 11b, each connected, at one end thereof, connected to a power node; N channel MOS transistors 16 and 17 each having a drain connected to the other end of the resistance element 11a and a gate receiving the feedback signal FBB, FBA; and an N channel MOS transistor 18 having a drain connected to the resistance element 11b and having a gate receiving a reference voltage Vr supplied through a terminal 5. The sources of these MOS transistors 16-18 are connected together.
The latch circuit LT1 further includes: an N channel MOS transistor 12 having a drain connected to a common source node of the MOS transistors 16-18, and a gate receiving the input signal IN supplied through a terminal 7; an N channel MOS transistor 19 having a drain connected to the common drain node of the MOS transistors 16 and 17, and a gate connected to the drain of the MOS transistor 18; an N channel MOS transistor 20 having a drain connected to the drain of the MOS transistor 18, a gate connected to the common drain node of the MOS transistors 16 and 17, and a source connected to the source of the MOS transistors 19; an N channel MOS transistor 13 having a drain connected to the common source node of the MOS transistors 19 and 20, a source connected to the source of the MOS transistor 12, and a gate receiving the complementary input signal ZIN supplied through a terminal 6; and an N channel MOS transistor 4 connected between the common source node of the MOS transistors 12 and 13 and a ground node and having a gate receiving a constant voltage Vc supplied through a terminal 8.
The MOS transistor 4 functions as a current source transistor and had its supplying current determined by the constant voltage Vc supplied to the gate thereof. The MOS transistors 12 and 13 conduct the current complementarily in accordance with the input signals IN and ZIN. The sources of the MOS transistors 16-18 are connected together, and a current flows through the MOS transistor receiving the highest gate voltage. The circuit.structure in which a MOS transistor receiving the highest gate voltage among MOS transistors having their sources connected together, flows substantially all the current as described above is referred to as a xe2x80x9csource coupled logicxe2x80x9d hereinafter.
The reference voltage Vr supplied to the MOS transistor 18 is set to a criterion voltage level for determining the H level and the L level of the feedback signals FBB and FBA supplied to the gates of the MOS transistors 16 and 17, and is normally set to a middle voltage level between the H and L voltage levels.
The MOS transistors 19 and 20 constitute a xe2x80x9csource coupled logicxe2x80x9d when the MOS transistor 13 is made conductive, and latch the output signals of the MOS transistors 16-18 due to the structure that their gates and drains are cross-coupled.
Similarly to the latch circuit LT1, the latch circuit LT2 includes: resistance elements 11c and 11d each having one end connected to the power node; an N channel MOS transistor 21 having a drain connected to the other end of the resistance element 11c and a gate connected to the drains of the MOS transistors 18 and 20; an N channel MOS transistor 22 having a drain connected to the other end of the resistance element 11d, a gate connected to the drains of the MOS transistors 16, 17 and 19, and a source connected to the source of the MOS transistor 21; an N channel MOS transistor 14 having a drain connected to the common source node of the MOS transistors 21 and 22 and a gate receiving the input signal ZIN applied from the terminal 6; an N channel MOS transistor 23 having a drain connected to the drain of the MOS transistor 21 and a gate connected to the drains of the MOS transistors 22 and 24; an N channel MOS transistor 24 having a drain connected to the drain of the MOS transistor 22, a gate connected to the drains of the MOS transistors 21 and 23, and a source connected to the source of the MOS transistor 23; an N channel MOS transistor 15 having a drain connected to the common source node of the MOS transistors 23 and 24, a source connected to the source of the MOS transistor 14 and a gate receiving the input signal IN; and a current source N channel MOS transistor 4b connected between the common source node of the MOS transistors 14 and 15 and the ground node and having a gate receiving the constant voltage Vc supplied through the terminal 8.
MOS transistors 23 and 24 have their gates and drains cross-coupled, to latch output signals of the MOS transistors 21 and 22 when the MOS transistors 23 and 24 are active.
This latch circuit LT2 takes in complementary output signals of the latch circuit LT1 when the input signal ZIN is at an H level, and latches the complementary signals when the input signal IN turns into an H level. Accordingly, the latch circuit LT2 transfers the output signals of the latch circuit LT1 with delay of a half of one cycle of the input signal IN, to output the signals to the output terminals 9 and 10.
The flip-flop 2 also includes two cascaded latch circuits LT3 and LT4 to perform transfer/latch operation complementarily to each other in response to the input signals IN and ZIN. The latch circuits LT3 and LT4 in this flip-flop 2 have the same structure as the latch circuit LT2. In accordance with the input signals IN and ZIN, the latch circuits LT3 and LT4 transfer and latch the complementary output signals (actual output signals OUT and OUTB of the frequency divider) of the latch circuit LT2.
The flip-flop 3 also includes latch circuits LT5 and LT6 to perform transfer/latch operation complementarily to each other in response to the input signals IN and ZIN. The latch circuits LT5 has the same structure as the latch circuits LT2-LT4 have. This latch circuit LT5 takes in complementary output signals of the latch circuit LT4 in the flip-flop 2 when the input signal ZIN is at an H level, and latches the complementary signals when the input signal IN turns into an L level.
The latch circuit LT6 at the last stage is further provided with components for changing the frequency division ratio. Specifically, the latch circuit LT6 includes: resistance elements 11e and 11f for pulling up output signals; N channel MOS transistors 31 and 30 constituting a differential stage, and connected to the respective resistance elements 11e and 11f and having gates receiving the complementary output signals of the latch circuit LT5, respectively; a resistance element 36 connected to the common source node of the MOS transistors 30 and 31; an N channel MOS transistor 41 having a drain connected to the resistance element 36 and a gate receiving the input signal ZIN from the terminal 6; N channel MOS transistors 28 and 29 for latching drain voltages of the MOS transistors 31 and 30; a resistance element 37 connected to the common source node of the MOS transistors 28 and 29; an N channel MOS transistor 42 connected to the resistance element 37 in series and having a gate receiving the input signal IN; and an N channel MOS transistor 4c connected between the common source node of the MOS transistors 41 and 42 and the ground node, and having a gate receiving the constant voltage Vc.
The gates of the N channel MOS transistors 28 and 29 are connected to the drains of the MOS transistors 31 and 30, respectively. The drains of the MOS transistors 28 and 29 are connected to the drains of the MOS transistors 30 and 31, respectively. Thus, the transistors 28 and 29 drive the output nodes thereof in accordance with the complementary output signals of the latch circuit LT6. The feedback signal FBB is outputted from the common drain node of the MOS transistors 29 and 31.
The MOS transistor 4c receives the constant voltage Vc at a gate thereof to operate as a constant current source transistor. Therefore, the operating current of this latch circuit LT6 is determined by the constant voltage Vc.
The latch circuit LT6 is further provided N channel MOS transistors 25 and 26 for stopping the transfer/latch operation of the latch circuit LT6 when rendered conductive. N channel MOS transistor 25 has its drain connected to the drains of the N channel MOS transistors 29 and 31, and its source connected to a connection node between the resistance element 36 and the MOS transistor 41. N channel MOS transistor 26 has its drain connected to the drains of the MOS transistors 29 and 31, and its source connected to a connection node between the resistance element 37 and the MOS transistor 42.
These MOS transistors 25-31 have the same size (the ratio of the channel width to the channel length), so that they have the same current supplying capability when their gate voltages are the same. The resistance elements 36 and 37 are provided in order to reliably render the MOS transistors 25 and 26 conductive, regardless of the voltage level of the input signals of the latch circuit LT6, when the MOS transistors 25 and 26 are rendered conductive. The resistance elements 36 and 37 make the source voltage of the MOS transistors 28-31 higher than that of the MOS transistors 25 and 26. MOS transistors 25 and 26 have the gate to source voltage thereof made larger than those of the MOS transistors 28-31, when made conductive. Accordingly, the current surely flows through the MOS transistors 25 and 26 in this state.
The output signal of the latch circuit LT4 is applied as the feedback signal FBA to the gate of the MOS transistor 17 in the latch circuit LT1. The output signal of the latch circuit LT6 is applied as the feedback signal FBB to the gate of the MOS transistor 16 in the latch circuit LT1. Now, the operation of the frequency divider shown in FIG. 13 will be described in the following, referring to FIGS. 14 and 15.
First, referring to FIG. 14, the operation in the case that a division ratio switching signal SEL is set to an H level, will be described.
When the division ratio switching signal SEL is set to an H level, the voltage at the H level of the signal SEL is a higher voltage level (for example, a power supply voltage VDD) than the voltage level of the output signals of the latch circuit LT5. When the input signal IN is at an L level and the input signal ZIN is at an H level, the MOS transistors 41 and 42 are on and off, respectively. Therefore, comparing operation is performed by the MOS transistors 25, 30 and 31. The resistance element 36 is connected to the sources of the MOS transistors 30 and 31. Thus, even if the gate voltage at one of these MOS transistors 30 and 31 attains an H level by the output signal of the latch circuit LT5, its gate to source voltage Vgs is lower than the gate to source voltage of the MOS transistors 25. Accordingly, substantially all the current is supplied to the MOS transistor 41 through the MOS transistor 25. Thus, the voltage level of the drain of the MOS transistor 31 is set to an L level so that the feedback signal FBB is set to an L level.
When the input signal IN is at an H level, the MOS transistor 42 turns on so that the circuit formed of the MOS transistors 26, 28 and 29 operates. In this case, the gate to source voltage of the MOS transistor 26 is larger than the gate to source voltage of each of the MOS transistors 28 and 29 due to the resistance element 37. Similarly, substantially all the current flows through the MOS transistor 26, so that the drain voltage of the MOS transistor 29 attains an L level. Accordingly, when the division ratio switching signal SEL is set to an H level, current flows constantly through the MOS transistors 25 and 26, so that the feedback signal FBB is fixed to an L level.
In the flip-flop 1, the MOS transistors 16 and 17 in the latch circuit LT1 constitute an OR circuit. Therefore, when the gate voltage of the MOS transistor 16 is at an L level, current flows through either one of the MOS transistors 17 and 18 in accordance with the logic (voltage) level of the feedback signal FBA. Thus, a structure equivalent to the structure in which the flip-flops 1 and 2 are connected to each other through a feedback path is provided to implement 1/4 frequency-dividing operation.
Specifically, when the input signal IN is at an H level, current having a magnitude determined by the current source transistor 4a flows through the MOS transistor 12. When the voltage level of the feedback signal FBA is higher than the reference voltage Vr, current flows through MOS transistor 17 and current hardly flows through the MOS transistor 18, due to a source coupled logic structure. Therefore, output signal QA of the latch circuit LT1, the voltage at the drain node of the MOS transistor 18, attains an H level equal to the power supply voltage VDD. Conversely, when the feedback signal FBA is at an L level and is lower than the reference voltage Vr, current flows through the MOS transistor 18, so that the output signal QA of the latch circuit Lt1 attains an L level.
When the input signal IN attains an L level and the complementary signal attains an H level, the MOS transistor 12 is turned off and the MOS transistor 13 is turned on. The MOS transistors 19 and 20 compare the drain voltages of the MOS transistors 18 and 19 with each other, and drive the output signal QA in accordance with the result of comparison. When the output signal QA is at an H level, for example, current flows through the MOS transistor 19. On the other hand, the MOS transistor 20 maintains the off state, so that the output signal QA is kept at the H level. That is, the output signal QA of the latch circuit LT1 is latched by the MOS transistors 19 and 20.
When the output signal QA is at an L level, current flows through the MOS transistor 20 from the resistance element 11b having a predetermined resistance value, so that the output signal QA is kept at the L level. In other words, when the input signal IN is at an H level and the MOS transistor 12 is on, the feedback signal FBA is taken in the latch circuit LT. When the input signal ZIN attains an H level, the taken-in signal is latched by the MOS transistors 19 and 20.
In the latch LT2, the same operation is performed. The latch circuit LT1 takes in the complementary signals OUT and ZOUT in accordance with the input signal ZIN. Then, the input signal ZIN attains an H level so that a latch state is implemented. Specifically, when the input signal ZIN turns into an H level, current supplied through either one of the resistance elements 11c and 11d flows through either one of the MOS transistors 21 and 22. The drain voltages of these MOS transistors 21 and 22 are determined by the voltage level of the output signal QA of the latch circuit LT1. In this state, the MOS transistor 15 is off, and no current flows through the MOS transistors 23 and 24.
Thereafter, when the input signal ZIN turns into an L level, no current flows through the MOS transistors 21 and 22 so that the taking-in of the output signal of the latch circuit LT1 is stopped. On the other hand, the MOS transistor 15 turns on so that the cross-coupled differential stage composed of the MOS transistors 23 and 24 is activated. Responsively, the output signals OUT and OUTB of the latch circuit LT2 are latched.
In the flip-flop 1, therefore, the feedback signal FBA is taken into the latch circuit LT1 when the input signal IN is at an H level. When the input signal IN turns into an L level, this taken-in signal is latched in the flip-flop 1 and transferred to the latch circuit LT2 at the next stage. When the input signal IN turns into an L level and the complementary input signal ZIN turns into an H level, the output signal QA of the latch circuit LT1 is taken into the latch circuit LT2. Subsequently, when the complementary input signal ZIN turns into an L level, the taken-in output signal of the latch circuit LT1 is latched in the latch circuit LT2.
In other words, the latch circuits LT1 and LT2 perform transfer and latch operation complementarily to each other. As a whole, the flip-flop 1 takes in the feedback signal FBA in accordance with the input signal IN, and outputs this taken-in feedback signal after a half cycle of the input signal IN elapses.
In the flip-flop 2, in the same way, the latch circuits LT3 and LT4 perform transfer/latch operation in accordance with the input signals IN and ZIN. When the latch circuit LT2 is in a latch state, the latch circuit LT3 performs taking-in operation. When the latch circuit LT2 performs transfer operation (taking-in operation), the latch circuit LT3 is in a latch state. The latch circuit LT4 performs transfer/latch operation complementarily to the latch circuit LT3. Therefore, this flip-flop 2 outputs the output signal of the flip-flop 1 after a half cycle of the input signal IN elapses.
The flip-flops 1 and 2 cause the output signal OUT and the fed-back signal FBA each to change with delay of one cycle of the input signal IN from the change of the other. Specifically, the output signal OUT changes after one cycle of the input signal IN from the change of the feedback signal FBA. After one cycle of the input signal IN from the change of the output signal OUT, the feedback signal FBA changes. Therefore, each of the feedback signal FBA and the output signal OUT changes every time when two cycles of the input signal IN elapse. Thus, this output signal OUT has a period 4T which is four times as long as a period T of the input signal IN. That is, the frequency of the output signal OUT is one-fourth times that of the input signal IN, so that 1/4 frequency division is realized.
Now, the operation in the case that the division ratio switching signal SEL is set to an L level will be described in the following, referring to FIG. 15. L level of the division ratio switching signal SEL is such a voltage level that the MOS transistors 25 and 26 in the flip-flop 3 are kept off regardless of the voltage levels of the output signals of the latch circuit LT5 in the flip-flop 3. In this case, the MOS transistors 28-31 in the latch circuit LT5 turns on or off in accordance with the output signals of the latch circuit LT5. Therefore, the feedback signal FBB changes in accordance with the output signal of the latch circuit LT5.
When the input signal IN is at an H level, the MOS transistors 16 and 17 turn off when the feedback signals FBA and FBB are both at L level. Thus, current flows through the MOS transistor 18 so that the output signal QA of the latch circuit LT1 attains an L level. When the input signal ZIN turns into an H level, the latch circuit LT2 takes in and latches the output signal QA from the latch circuit LT1. Accordingly, the output signal OUT rises up to an H level in response to the rise of the complementary input signal ZIN. The output signal OUT is successively transferred to the latch circuits LT3 and LT4 in the flip-flop 2 in accordance with the input signal IN. The feedback signal FBA changes with delay of one cycle of the input signal IN in response to the output signal OUT.
When the feedback signal FBA attains an H level, the MOS transistor 17 turns on and no current flows through the MOS transistors 16 and 18. Therefore, when the input signal IN attains an H level, the output signal QA of this latch circuit LT1 turns to an H level so that the output signal OUT falls down to an L level in response to the next rise of the complementary input signal ZIN to an H level.
On the other hand, the feedback signal FBA outputted from the latch circuit LT4 in the flip-flop 2 is transferred to the latch circuits LT5 and LT6 in the flip-flop 3 in accordance with the input signals IN and ZIN. Therefore, the feedback signal FBB changes in response to the feedback signal FBA, with delay of one cycle of the input signal IN. Therefore, even if the feedback signal FBA is transitioned into an L level with delay of one cycle of the input signal IN from the transition of the output signal OUT to an L level, the feedback signal is at an H level. When the input signal IN turns into an H level in this state, the MOS transistor 16 is turned on and the MOS transistors 17 and 18 are turned off and the output signal QA of the latch circuit LT1 is maintained at the H level. That is, the H-level period of the output signal QA is made longer owing to this feedback signal FBB. Since the feedback signal FBB changes with delay of one cycle from the feedback signal FBA, the time period during which the output signal QA of the latch circuit LT1 is at the H level is made longer by one cycle of the input signal IN, as compared to the case when frequency 1/4-dividing operation is performed.
When the feedback signals FBA and FBB both turn into L levels, the output signal QA of the latch circuit LT1 attains an L level in response to the rise of the input signal IN to an H level. Thus, the output signal OUT turns into an H level after a half cycle of the input signal IN. The feedback signal FBA changes into an H level with delay of one cycle with respect to the output signal OUT. Consequently, the output signal QA of the latch circuit LT1 changes again from the L level to an H level.
Therefore, the H level period of the output signal OUT is equal to two cycles of the input signal IN and the L level period thereof is equal to three cycles of the input signal IN, so that the output signal OUT has a period 5T five times as long as the period T of the input signal IN.
In other words, by the flip-flop 3, the feedback signal FBB is transmitted to the first stage flip-flop with delay of one cycle of the input signal IN with respect to the feedback signal FBA. Thus, on the basis of the feedback signals FBA and FBB, current flows through one of the MOS transistors 16 and 17 so that the period during which the MOS transistor 18 is off becomes longer by one cycle of the input signal IN. Consequently, the cycle of the output signal OUT can be made longer. In this way, a frequency divider for performing frequency 1/5-dividing operation is realized.
As shown in FIG. 13, the flip-flops 1-3 can be operated at a high speed, owing to current driving, by using the xe2x80x9csource coupled logicxe2x80x9d composed of the differential transistors having their sources connected together to perform comparing operation and transferring a feedback signal in accordance with an input signal in the frequency divider. Thus, even if the input signal IN is a high-speed signal, accurate frequency division can be performed to generate a frequency divided signal having a desired division ratio.
For a frequency divider as described above, sub-micron processing can be achieved through a CMOS process. Thus, it is possible to make the size of transistor elements miniaturized, to implement a frequency divider operable at high speed with low power consumption. By using the xe2x80x9csource coupled logicxe2x80x9d, high-speed operation can be achieved due to no need of full swing of the gate voltages of the differential transistors. By using, in a latching stage, the same structure as in input differential stages, the output signal having an intermediate voltage level of the differential stage can be reliably latched.
However, the feedback signals FBA and FBB each are a single end signal, and if they are small amplitude signals, such a problem arises that an influence of noises increases. H level of the feedback signals FBA and FBB is the level of the power supply voltage VDD and L level thereof is the level of the voltage VDDxe2x88x92Rxc2x7Ib, wherein R represents the resistance value of the resistance elements 11 (11a-11f), and Ib represents the value of current flowing through the resistance elements 11 (11a-11f). Therefore, if the resistance value and/or the current value are made large, the amplitude of the feedback signals FBA and FBB can be made large. However, in the case that the resistance values of the resistance elements 11a-11f are made large, the transition speed of the output signal becomes slow upon operation. Thus, it becomes impossible to realize a frequency divider that can operate at a high speed.
When the current Ib flowing through the resistance elements 11(11a-11f) is made large, current flows constantly through the current source transistors 4a-4c and 4, independent of whether the input signal IN is at an H level or at an L level, causing a problem of increased current dissipation.
In order to change the division ratio of this frequency divider in accordance with the division ratio switching signal SEL, the MOS transistors 25 and 26 are used. These MOS transistors 25 and 26 have the same size (the ratio between the channel width to the channel length) as the MOS transistors 28-31 constituting the differential stages in the latch circuit LT6. When the feedback signal is set to an L level, it is necessary to flow a current constantly through the MOS transistors 25 and 26 when the associated current source transistors 41 and 42 are made conductive. The MOS transistors 28-31 have the same size (the ratio between the channel width and the channel length). The source voltages of the MOS transistors 28-31 are made high by the resistance elements 36 and 37, to ensure a larger amount of current to flow through the MOS transistors 25 and 26 by the division ratio switching signal SEL to set the feedback signal FBB to the L level.
In this case, however, current flows through the MOS transistors 28 and 30 when the MOS transistors 41 and 42 are made conductive. Therefore, the amplitude of the feedback signals FBB becomes small. In order to make the amplitude of the feedback signal FBB adequately large and to set the feedback signal FBB reliably to an L level, it is necessary to make the resistance values of the resistance elements 11a and 11f large. Thus, a problem that speed performance is lowered arises. Since the source voltages of the MOS transistors 28-31 are made high with the resistance elements 36 and 37, the MOS transistors 28-31 do not correctly operate if the voltage level of the power supply voltage VDD is lowered. Thus, there arises a problem that the power supply voltage VDD cannot be lowered, resulting in a difficulty in reducing the power supply voltage.
The following problem would also be caused. When the amplitude of the feedback signals FBA and FBB is made large for transference, it takes much time to charge and discharge a feedback path so that propagation delay in this path becomes large. As a result, a frequency divider that can operate at a high speed cannot be implemented.
An object of the present invention is to provide a variable frequency divider circuit that operates stably at high speed with a low consumption power and is superior in noise immunity.
Another object of the present invention is to provide a variable frequency divider circuit, suitable for the CMOS process, operates stably at a high speed.
The variable frequency divider circuit according to the present invention includes: a plurality of latch circuits cascaded in K stages, with K being an integer of 3 or more, each for performing transfer and latch in accordance with a divided signal; and a mode setting transistor for fixing the voltage level of an output signal of the K-th stage latch circuit in response to a mode setting signal. The K-th stage latch circuit and the (K-2)-th latch circuit feed back each output signal to the first stage latch circuit among the latch circuits of K stages. The mode setting transistor has a larger current driving capability than that of transistors for driving a feedback path (FBB) of the K-th stage latch circuit.
The variable frequency divider according to a second aspect of the present invention includes: latch circuits of K stages with K being an integer of 3 or more, each for performing transference and latching in accordance with an input signal; and a mode setting transistor for fixing a voltage level of differential output signals of a K-th stage latch circuit in response to a mode setting signal. Each of the K-th stage latch circuit and the (K-2)-th latch circuit feeds back differential output signals to the first stage latch circuit.
The variable frequency divider according to a third aspect of the present invention includes: latch circuits, cascaded in K stages with K being an integer of 3 or more, each for performing transference and latching in accordance with an input signal; and a mode setting transistor for fixing a voltage level of differential output signals of a K-th stage latch circuit in response to a mode setting signal. Each of the K-th latch circuit and the (K-2)-th latch circuit feeds back differential output signals to the first stage latch circuit among the cascaded latch circuits. The mode setting transistor has a larger current driving capability than that of transistors for driving a feedback path of the K-th stage latch circuit.
The variable frequency divider according to a fourth aspect of the present invention includes: latch circuits, cascaded in K stages with K being an integer of 3 or more, each for performing transference and latching in accordance with an input signal. Each of the K-th stage latch circuit and the (K-2)-th stage latch circuit feeds back differential output signals to the first stage latch circuit among the cascaded latch circuits. A circuit section for outputting the feedback output signals of the K-th and (K-2)-th stage latch circuits is arranged adjacently to an area where the first stage latch circuit is arranged.
By making the current driving capability of the mode setting transistor for switching the division ratio larger than that of the transistors for driving the feedback path, a larger amount of current can flow constantly through the mode setting transistor than the feedback path driving transistors when the mode setting transistor is rendered conductive. Thus, the voltage level of feedback signals can be reliably set to a desired level.
By using differential signals as the feedback signal, the amplitude of the feedback signal can be made adequately large and the feed back signal can be transferred to the first stage latch circuit even when the feedback signal is a single end feedback signal having a small amplitude. Thus, the feedback signal having a small amplitude can be correctly transferred under a low power supply voltage condition.
Moreover, by combining these aspects, a frequency divider that operates stably at a high speed with a low consumption current, can be realized.
By arranging circuits for transmitting and receiving the feedback signal adjacently to each other, the length of the feedback path can be made short. Additionally, the feedback signal can be transferred at a high speed and current for driving the feedback path can be reduced. Thus, a frequency divider that operates at a high speed with a low consumption current, can be realized.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.